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authorGravatar Gustavo Zacarias <gustavo@zacarias.com.ar>2015-03-03 12:52:30 -0300
committerGravatar Thomas Petazzoni <thomas.petazzoni@free-electrons.com>2015-03-04 22:16:41 +0100
commit50451998f0e39d46675e9b1638ed4e38aae3ceba (patch)
tree15862bbae00c43e2ef1004cb686cfcdf26991590 /arch
parent4274f758ed2b2f9a1440b3f8e4c8bae25786e807 (diff)
downloadbuildroot-50451998f0e39d46675e9b1638ed4e38aae3ceba.tar.gz
buildroot-50451998f0e39d46675e9b1638ed4e38aae3ceba.tar.bz2
arch: add support for AMD steamroller
Add support for AMD steamroller optimizations, available in gcc 4.8+ as bdver3. Signed-off-by: Gustavo Zacarias <gustavo@zacarias.com.ar> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/Config.in.x8611
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index 8a844dbe94..d5788b1233 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -139,6 +139,15 @@ config BR2_x86_jaguar
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
+config BR2_x86_steamroller
+ bool "steamroller"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
config BR2_x86_geode
bool "geode"
# Don't include MMX support because there several variant of geode
@@ -189,6 +198,7 @@ config BR2_ARCH
default "i686" if BR2_x86_opteron_sse3 && BR2_i386
default "i686" if BR2_x86_barcelona && BR2_i386
default "i686" if BR2_x86_jaguar && BR2_i386
+ default "i686" if BR2_x86_steamroller && BR2_i386
default "i686" if BR2_x86_k6
default "i686" if BR2_x86_k6_2
default "i686" if BR2_x86_athlon
@@ -221,6 +231,7 @@ config BR2_GCC_TARGET_ARCH
default "k8-sse3" if BR2_x86_opteron_sse3
default "barcelona" if BR2_x86_barcelona
default "btver2" if BR2_x86_jaguar
+ default "bdver3" if BR2_x86_steamroller
default "k6" if BR2_x86_k6
default "k6-2" if BR2_x86_k6_2
default "athlon" if BR2_x86_athlon