aboutsummaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorGravatar Esben Haabendal <esben@geanix.com>2019-06-11 10:44:09 +0200
committerGravatar Peter Korsgaard <peter@korsgaard.com>2019-06-13 21:09:51 +0200
commit97651ce275198ed650da7944b967d93a79127bd9 (patch)
treeb7d4682bc71b4d508942610ea4efeb9b31bacc7e /arch
parent033844c44df13da70d9ca19e4ad057b9e730aef6 (diff)
downloadbuildroot-97651ce275198ed650da7944b967d93a79127bd9.tar.gz
buildroot-97651ce275198ed650da7944b967d93a79127bd9.tar.bz2
arch: Add support for Westmere targets
The westmere line of x86_64 targets lies between nehalem (corei7) and sandybridge (corei7-avx). Allowing use of -march=westmere enables use of AES instruction set on these targets. Signed-off-by: Esben Haabendal <esben@geanix.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/Config.in.x8611
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/Config.in.x86 b/arch/Config.in.x86
index 3f6983ac1b..eb655adbca 100644
--- a/arch/Config.in.x86
+++ b/arch/Config.in.x86
@@ -101,6 +101,15 @@ config BR2_x86_corei7
select BR2_X86_CPU_HAS_SSSE3
select BR2_X86_CPU_HAS_SSE4
select BR2_X86_CPU_HAS_SSE42
+config BR2_x86_westmere
+ bool "westmere"
+ select BR2_X86_CPU_HAS_MMX
+ select BR2_X86_CPU_HAS_SSE
+ select BR2_X86_CPU_HAS_SSE2
+ select BR2_X86_CPU_HAS_SSE3
+ select BR2_X86_CPU_HAS_SSSE3
+ select BR2_X86_CPU_HAS_SSE4
+ select BR2_X86_CPU_HAS_SSE42
config BR2_x86_corei7_avx
bool "corei7-avx"
select BR2_X86_CPU_HAS_MMX
@@ -235,6 +244,7 @@ config BR2_ARCH
default "i686" if BR2_x86_nocona && BR2_i386
default "i686" if BR2_x86_core2 && BR2_i386
default "i686" if BR2_x86_corei7 && BR2_i386
+ default "i686" if BR2_x86_westmere && BR2_i386
default "i686" if BR2_x86_corei7_avx && BR2_i386
default "i686" if BR2_x86_core_avx2 && BR2_i386
default "i686" if BR2_x86_atom && BR2_i386
@@ -271,6 +281,7 @@ config BR2_GCC_TARGET_ARCH
default "corei7-avx" if BR2_x86_corei7_avx
default "core-avx2" if BR2_x86_core_avx2
default "atom" if BR2_x86_atom
+ default "westmere" if BR2_x86_westmere
default "silvermont" if BR2_x86_silvermont
default "k8" if BR2_x86_opteron
default "k8-sse3" if BR2_x86_opteron_sse3