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authorGravatar Thomas De Schampheleire <thomas.de_schampheleire@nokia.com>2019-01-30 21:12:23 +0100
committerGravatar Thomas Petazzoni <thomas.petazzoni@bootlin.com>2019-02-04 17:30:06 +0100
commitb21e159b5da31afaca63fba228a620f74b317c88 (patch)
tree5d87318caa3d75a36d92e6fdf16b5551a8d314ba /arch
parentc49d446767b3c67820fc76026c9df7b7aa4ae9ee (diff)
downloadbuildroot-b21e159b5da31afaca63fba228a620f74b317c88.tar.gz
buildroot-b21e159b5da31afaca63fba228a620f74b317c88.tar.bz2
arch/mips: add (Marvell) Octeon II processor
The compiler recognizes a specific 'march' value for Octeon II processors, so create a 'Target Architecture Variant' entry for it in the target menu. Signed-off-by: Thomas De Schampheleire <thomas.de_schampheleire@nokia.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/Config.in.mips8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/Config.in.mips b/arch/Config.in.mips
index f28113df44..b8567c56b8 100644
--- a/arch/Config.in.mips
+++ b/arch/Config.in.mips
@@ -122,6 +122,13 @@ config BR2_mips_i6400
depends on BR2_ARCH_IS_64
select BR2_MIPS_CPU_MIPS64R6
select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
+config BR2_mips_octeon2
+ bool "Octeon II"
+ depends on BR2_ARCH_IS_64
+ select BR2_MIPS_CPU_MIPS64R2
+ help
+ Marvell (formerly Cavium Networks) Octeon II CN60XX
+ processors.
config BR2_mips_p6600
bool "P6600"
depends on BR2_ARCH_IS_64
@@ -241,6 +248,7 @@ config BR2_GCC_TARGET_ARCH
default "mips64r5" if BR2_mips_64r5
default "mips64r6" if BR2_mips_64r6
default "i6400" if BR2_mips_i6400
+ default "octeon2" if BR2_mips_octeon2
default "p6600" if BR2_mips_p6600
config BR2_MIPS_OABI32